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M2GL005-FGG484I Programmable Logic ICs 209 719872 6060 484-BGA

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M2GL005-FGG484I Programmable Logic ICs 209 719872 6060 484-BGA

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Brand Name :	Microchip Technology
Model Number :	M2GL005-FGG484I
Price :	Negotiable
Supply Ability :	1000000pcs

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M2GL005-FGG484I Programmable Logic ICs 209 719872 6060 484-BGA

M2GL005-FGG484I IGLOO2 Field Programmable Gate Array (FPGA) IC 209 719872 6060 484-BGA

Microchip Technology IGLOO®2 Field-Programmable Gate Arrays (FPGAs)

Microchip Technology IGLOO®2 Field-Programmable Gate Arrays (FPGAs) are ideal for general-purpose functions such as Gigabit Ethernet or dual PCI Express® control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing, system management, and secure connectivity. They are used in applications for the communications, industrial, medical, defense and aviation markets.

The IGLOO2 architecture offers up to 3.6x gate count implemented with the 4-input look-up table (LUT) fabric with carry chains, giving 2x performance, and includes multiple embedded memory options and mathblocks for digital signal processing (DSP). High-speed serial interfaces include PCI express (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS), plus native serialization/deserialization (SerDes) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide high-speed memory interfaces.

FEATURES

High-Performance FPGA
- Efficient 4-input LUTs with carry chains for high-performance and low power
- Up to 236 blocks of dual-port 18KBit SRAM (Large SRAM) with 400MHz synchronous performance (512 x 36, 512 x 32, 1KBit x 18, 1KBit x 16, 2KBit x 9, 2KBit x 8, 4KBit x 4, 8KBit x 2, or 16KBit x 1)
- Up to 240 blocks of three-port 1KBit SRAM with 2 read ports and 1 write port (micro SRAM)
- High-performance DSP
  - Up to 240 fast mathblocks with 18 x 18 signed multiplication, 17 x 17 unsigned multiplication and 44-bit accumulator
High-Speed Serial Interfaces
Up to 16 SerDes lanes, each supporting:
- XGXS/XAUI extension (to implement a 10 Gbps (XGMII) Ethernet PHY interface)
- Native EPCS SerDes interface facilitates implementation of serial rapidIO in fabric or an SGMII interface to a soft Ethernet MAC
- PCI express (PCIe) endpoint controller
- x1, x2, and x4 lane PCI express core
- Up to 2KBytes maximum payload size
High-Speed Memory Interfaces
- Up to 2 high-speed DDRx memory controllers
  - HPMS DDR (MDDR) and fabric DDR (FDDR) controllers
  - Supports LPDDR/DDR2/DDR3
  - Maximum 333MHz clock rate
  - SECDED enable/disable feature
  - Supports various DRAM bus width modes, x8, x9, x16, x18, x32, and x36
  - Supports command reordering to optimize memory efficiency
  - Supports data reordering, returning critical word first for each command
- SDRAM support through a soft SDRAM memory controller
High-Performance Memory Subsystem
- 64KB embedded SRAM (eSRAM)
- Up to 512KB embedded nonvolatile memory (eNVM)
- One SPI/COMM_BLK
- DDR bridge (2 port data R/W buffering bridge to DDR memory) with 64-bit AXI interface
- Non-blocking, multi-layer AHB bus matrix allowing multi-master scheme supporting 5 masters and 7 slaves
- Two AHB/APB interfaces to FPGA fabric (master/slave capable)
- Two DMA controllers to offload data transactions
  - 8-channel peripheral DMA (PDMA) for data transfer between HPMS peripherals and memory
- High-performance DMA (HPDMA) for data transfer between eSRAM and DDR memories
Clocking Resources
- Clock sources
  - High precision 32 kHz to 20MHz main crystal oscillator
  - 1MHz embedded RC oscillator
  - 50MHz embedded RC oscillator
- Up to 8 clock conditioning circuits (CCCs) with up to 8 integrated analog PLLs
  - Output clock with 8 output phases and 45° phase difference (multiply/divide, and delay capabilities)
- Frequency: input 1MHz to 200MHz, output 20MHz to 400MHz

Operating Voltage and I/Os
- 1.2V core voltage
- Multi-standard user I/Os (MSIO/MSIOD)
  - LVTTL/LVCMOS 3.0V (MSIO only)
  - LVCMOS 2.0V, 1.5V, 1.8V, and 2.5V
  - DDR (SSTL2_1and SSTL2_2)
  - LVDS, MLVDS, Mini-LVDS, and RSDS differential standards
  - PCI
  - LVPECL (receiver only)
- DDR I/Os (DDRIO)
  - DDR, DDR2, DDR3, LPDDR, SSTL2, SSTL18, and HSTL
  - LVCMOS 2.0V, 1.5V, 1.8V, and 2.5V
- Market leading number of user I/Os with 5G SerDes
Security
- Design security features (available on all devices)
  - Intellectual property (IP) protection through unique security features and use models new to the PLD industry
  - Encrypted user key and bitstream loading, enabling programming in less-trusted locations
  - Supply-chain assurance device certificate
  - Enhanced anti-tamper features
  - Zeroization
- Data security features (available on premium devices)
  - Non-deterministic random bit generator (NRBG)
  - User cryptographic services (AES-256, SHA-256, elliptical curve cryptographic (ECC) engine)
  - User physically unclonable function (PUF) key enrollment and regeneration
  - CRI pass-through DPA patent portfolio license
  - Hardware firewalls protecting microcontroller subsystem (HPMS) memories
Reliability
- Single event upset (SEU) immune
  - Zero FIT FPGA configuration cells
- Junction Temperature
  - 125 °C - Military Temperature
  - 100 °C - Industrial Temperature
  - 85 °C - Commercial Temperature
- Single error correct double error detect (SECDED) protection on the following:
  - Embedded memories (eSRAMs)
  - PCIe buffer
  - DDR memory controllers with optional SECDED modes
- Buffers implemented with SEU resistant latches on the following:
  - DDR bridges (HPMS, MDDR, and FDDR)
  - SPI FIFO
  - NVM integrity check at power-up and on-demand
  - No external configuration memory required
  - Instant-on, retains configuration when powered off
Low Power
- Low static and dynamic power
  - Flash*Freeze (F*F) mode for fabric
- Power as low as 13mW/Gbps per lane for SerDes devices

APPLICATIONS

Wireless
Wireline
Industrial networking and control

System management
Secure wireless
Defense and aviation

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